RISC architectures typically include a large, general purpose register file containing GPR operands, to minimize the need for repeated accesses to main memory. Superscaler architectures typically include an instruction dispatch unit that supplies instructions from an instruction queue to diverse parallel execution units, such as a fixed point unit, a floating point unit, a load/store unit, and other functional processing units.
Conventionally, the instruction dispatch unit in a superscaler computer issues two instructions in each cycle to two different execution units that can operate independently and in parallel. The instructions include an op code field that identifies the execution unit and the operation to be performed. The instructions also include fields specifying one or more GPR registers as sources of GPR operands and destinations of results for the operation to be performed. When the instruction dispatch unit is handling an instruction from the instruction queue, it decodes the op code to identify to which execution unit the instruction is to be dispatched. The instruction dispatch unit also signals the GPR to transfer the designated GPR operands to the identified execution unit. Some instructions designate two source GPR registers and thus the GPR has two read ports to enable the transfer of two operands during the same cycle to an execution unit.
If two consecutive instructions in the instruction queue are intended to go to the same execution unit, the second occurring instruction must be held by the instruction dispatch unit for dispatching in the next cycle. The instruction dispatch unit must therefore delay its handling of the third occurring instruction in the instruction queue until the third cycle.